The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 2026
Filed:
Sep. 24, 2021
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Kyle Mcelhinny, Tempe, AZ (US);
Bohan Shan, Chandler, AZ (US);
Hongxia Feng, Chandler, AZ (US);
Xiaoying Guo, Chandler, AZ (US);
Adam Schmitt, Tempe, AZ (US);
Jacob Vehonsky, Gilbert, AZ (US);
Steve Cho, Chandler, AZ (US);
Leonel Arana, Phoenix, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/60 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 24/14 (2013.01); H01L 21/60 (2021.08); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 23/5381 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 2021/60022 (2013.01);
Abstract
Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes operational bridge bumps to electrically connect the die to a bridge within the substrate. The apparatus also includes dummy bumps adjacent the operational bridge bumps.