The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2026

Filed:

Jun. 09, 2025
Applicant:

Deca Technologies Usa, Inc., Tempe, AZ (US);

Inventors:

Paul R. Hoffman, San Diego, CA (US);

Timothy L. Olson, Phoenix, AZ (US);

Craig Bishop, Scottsdale, AZ (US);

Robin Davis, Vancouver, WA (US);

Assignee:

Deca Technologies USA, Inc., Tempe, AZ (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/538 (2006.01); H01L 23/544 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 21/565 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/544 (2013.01); H01L 23/562 (2013.01); H01L 24/16 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54433 (2013.01); H01L 2224/16227 (2013.01);
Abstract

A method of making an interconnect substrate, comprising disposing an embedded component and at least one tracking identifier in a substrate core, and planarizing the substrate core to form a planar surface, forming a conductive layer over a frontside planar surface, disposing a layer of dielectric over the frontside planar surface, the embedded component, and the conductive layer, rotating the substrate core such that a back surface of the substrate core is configured for processing, and forming a conductive layer over the back surface of the substrate core.


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