The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2026

Filed:

Jul. 01, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Abhishek Sharma, Portland, OR (US);

Tahir Ghani, Portland, OR (US);

Anand Murthy, Portland, OR (US);

Wilfred Gomes, Portland, OR (US);

Sagar Suthram, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H10B 12/36 (2023.02);
Abstract

Integrated circuit dies, systems, and techniques are described herein related to three-dimensional dynamic random access memory. A memory device includes vertically aligned semiconductor structures coupled to independent gate structures, corresponding vertically aligned capacitors each coupled to a corresponding one of the semiconductor structures, and a bit line contact extending vertically across a depth of the semiconductor structures and coupled to each of the semiconductor structures.


Find Patent Forward Citations

Sharma, Abhishek. (2026). Three-dimensional dynamic random access memory with stacked semiconductor structures (U.S. Patent No. 12615762). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12615762

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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