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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12610582 B1

PDFFull Text
Date of Patent:
Apr. 21, 2026

Filed:

May. 12, 2022

Multi-layered source and drain contacts for a thin film transistor (tft) structure

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Abhishek Anil Sharma, Portland, OR (US);

Travis W. Lajoie, Forest Grove, OR (US);

Van H. Le, Beaverton, OR (US);

Timothy Jen, Portland, OR (US);

Kamal H. Baloch, Portland, OR (US);

Mark Armstrong, Portland, OR (US);

Albert B. Chen, Portland, OR (US);

Moshe Dolejsi, Portland, OR (US);

Shailesh Kumar Madisetti, Portland, OR (US);

Afrin Sultana, Portland, OR (US);

Deepyanti Taneja, Happy Valley, OR (US);

Vishak Venkatraman, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Arcane Law PLLC

Primary Examiner:

Nikolay K Yushin

Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 12/00 (2023.01); H10D 30/67 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6729 (2025.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 12/30 (2023.02); H10D 30/6713 (2025.01); H10D 30/6755 (2025.01);
Abstract

Techniques for forming thin film transistors (TFTs) having multilayer contact structures. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, and a conductive contact that contacts at least a portion of the semiconductor region. In some other cases, the conductive contact comprises a multilayer structure having at least a first material layer on the at least a portion of the semiconductor region, at least a second material layer on the first material layer, and a conductive fill material over the first and second material layers. In some other cases, the conductive contact comprises a multilayer structure having (1) a graded material layer on the at least a portion of the semiconductor region and (2) a conductive fill material over the graded material layer, wherein the graded material layer comprises a concentration gradient of a given element.

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