The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2026

Filed:

Sep. 28, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ching-Wei Tsai, Hsinchu, TW;

Yu-Xuan Huang, Hsinchu, TW;

Kuan-Lun Cheng, Hsin-chu, TW;

Chih-Hao Wang, Baoshan Township, Hsinchu County, TW;

Min Cao, Hsinchu, TW;

Jung-Hung Chang, Changhua County, TW;

Lo-Heng Chang, Hsinchu, TW;

Pei-Hsun Wang, Kaohsiung, TW;

Kuo-Cheng Chiang, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H01L 21/02 (2006.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H10D 30/024 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 30/797 (2025.01); H10D 62/121 (2025.01); H10D 64/015 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 84/0158 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0172 (2025.01); H01L 21/02603 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 84/856 (2025.01);
Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base. The semiconductor device structure includes a first multilayer stack over the base. The first multilayer stack includes a first channel layer and a second channel layer over and spaced apart from the first channel layer. The semiconductor device structure includes a gate stack over the substrate. The gate stack wraps around the first multilayer stack. The semiconductor device structure includes an inner spacer layer between the second channel layer and the first channel layer and between the first channel layer and the base. The semiconductor device structure includes a bottom spacer over the base. The semiconductor device structure includes a first source/drain structure over the bottom spacer and connected to the second channel layer.


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