The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2026
Filed:
Mar. 28, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Cheng-Yu Kuo, Kaohsiung City, TW;
Yu-Ching Lo, Hsinchu City, TW;
Wei-Jie Huang, New Taipei City, TW;
Ching-Pin Yuan, Hsinchu City, TW;
Yi-Che Chiang, Hsinchu, TW;
Kris Lipu Chuang, Hsinchu City, TW;
Hsin-Yu Pan, Taipei, TW;
Yi-Yang Lei, Taichung City, TW;
Ching-Hua Hsieh, Hsinchu, TW;
Kuei-Wei Huang, Hsinchu City, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
A package structure includes a die, a first redistribution circuit structure, a first redistribution circuit structure, a second redistribution circuit structure, an enhancement layer, first conductive terminals, and second conductive terminals. The first redistribution circuit structure is disposed on a rear side of the die and electrically coupled to thereto. The second redistribution circuit structure is disposed on an active side of the die and electrically coupled thereto. The enhancement layer is disposed on the first redistribution circuit structure. The first redistribution circuit structure is disposed between the enhancement layer and the die. The first conductive terminals are connected to the first redistribution circuit structure. The first redistribution circuit structure is between the first conductive terminals and the die. The second conductive terminals are connected to the second redistribution circuit structure. The enhancement layer is between the second conductive terminals and the second redistribution circuit structure.