The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2026

Filed:

Dec. 21, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jiun-Ruey Chen, Hillsboro, OR (US);

Christopher Jezewski, Portland, OR (US);

John Plombon, Portland, OR (US);

Miriam Reshotko, Portland, OR (US);

Mauro Kobrinsky, Portland, OR (US);

Scott B. Clendenning, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/76807 (2013.01); H01L 21/76831 (2013.01); H01L 21/76879 (2013.01); H01L 23/53238 (2013.01); H01L 23/5328 (2013.01);
Abstract

Metallization interconnect structures, integrated circuit devices, and methods related to high aspect ratio interconnects are discussed. A self assembled monolayer is selectively formed on interlayer dielectric sidewalls of an opening that exposes an underlying metallization structure. A first metal is formed on the underlying metallization structure and within only a bottom portion of the self assembled monolayer. The exposed portion of the self assembled monolayer is removed and a second metal is formed over the first metal.


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