The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2026

Filed:

Feb. 20, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yi-Chen Lo, Zhubei, TW;

Ding-Kang Shih, New Taipei, TW;

Tsungyu Hung, Hsinchu, TW;

Chia-Ling Pai, Taichung, TW;

Pang-Yen Tsai, Jhubei, TW;

Li-Te Lin, Hsinchu, TW;

Pinyen Lin, Rochester, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/00 (2025.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02068 (2013.01); H01L 21/76843 (2013.01); H01L 21/76861 (2013.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 62/151 (2025.01); H10D 64/01 (2025.01); H10D 84/017 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); H01L 23/5226 (2013.01);
Abstract

In an embodiment, a method includes forming a first semiconductor fin and a second semiconductor fin over a front-side of a substrate; etching a first recess in the first semiconductor fin and a second recess in the second semiconductor fin; forming a first epitaxial region in the first recess and first epitaxial nodules along sidewalls of the first recess; forming a second epitaxial region in the second recess and second epitaxial nodules along sidewalls of the second recess; flowing first precursors to remove the first epitaxial nodules; depositing an interlayer dielectric over the first epitaxial region and the second epitaxial region; etching a first opening in the interlayer dielectric to expose the first epitaxial region; forming a first epitaxial cap on the first epitaxial region and third epitaxial nodules over the interlayer dielectric; and flowing second precursors to remove the third epitaxial nodules.


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