The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2026
Filed:
May. 12, 2022
Intel Corporation, Santa Clara, CA (US);
Van H. Le, Beaverton, OR (US);
Timothy Jen, Portland, OR (US);
Vishak Venkatraman, Portland, OR (US);
Shailesh Kumar Madisetti, Portland, OR (US);
Cheng Tan, Hillsboro, OR (US);
Harish Ganapathy, Portland, OR (US);
James Pellegren, Portland, OR (US);
Kamal H. Baloch, Portland, OR (US);
Abhishek Anil Sharma, Portland, OR (US);
INTEL CORPORATION, Santa Clara, CA (US);
Abstract
Techniques are provided herein for forming thin film transistor structures having co-doped semiconductor regions. The addition of insulating dopants can be used to improve the performance, stability, and reliability of the TFT. A given TFT structure within an array of similar TFT structures formed in an interconnect region may include a semiconductor region that is co-doped with one or more additional elements. The doping profile can be tuned to optimize performance, stability, and reliability of the TFT structure. In some embodiments, the doping profile causes an overall reduction in the conductivity of the semiconductor region, leading to a higher threshold voltage. Designing access devices (in, for example, a DRAM architecture) with higher threshold voltages can be beneficial for improving reliability of the memory cell.