logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12598757 B1

PDFFull Text
Date of Patent:
Apr. 07, 2026

Filed:

Feb. 02, 2023

Structure and formation method of package with hybrid interconnection

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Tsung-Fu Tsai, Changhua County, TW;

Szu-Wei Lu, Hsinchu City, TW;

Shih-Peng Tai, Xinpu Township, TW;

Chen-Hua Yu, Hsinchu City, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

McClure, Qualey & Rodack, LLP

Primary Examiner:

Niki H Nguyen

Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H10B 80/00 (2023.01);
U.S. Cl.
CPC ...
H10B 80/00 (2023.02); H01L 21/56 (2013.01); H01L 21/76898 (2013.01); H01L 23/3128 (2013.01); H01L 23/481 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/80 (2013.01); H01L 24/92 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/92125 (2013.01);
Abstract

A package structure and a formation method are provided. The method includes providing a semiconductor substrate and bonding a first chip structure on the semiconductor substrate through metal-to-metal bonding and dielectric-to-dielectric bonding. The method also includes bonding a second chip structure over the semiconductor substrate through solder-containing bonding structures. The method further includes forming a protective layer surrounding the second chip structure. A portion of the protective layer is between the semiconductor substrate and a bottom of the second chip structure.

Find Patent Forward Citations

Tsai, Tsung-Fu. (2026). Structure and formation method of package with hybrid interconnection (U.S. Patent No. 12598757). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12598757

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…