The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2026

Filed:

Jun. 30, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yi-Hsiung Lin, Zhubei City, TW;

Yi-Hsun Chiu, Zhubei City, TW;

Shang-Wen Chang, Jhubei City, TW;

Ching-Wei Tsai, Hsinchu City, TW;

Yu-Xuan Huang, Hsinchu, TW;

Kuan-Lun Cheng, Hsinchu, TW;

Chih-Hao Wang, Baoshan Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/85 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 48/36 (2025.01);
U.S. Cl.
CPC ...
H10D 84/85 (2025.01); H10D 30/031 (2025.01); H10D 30/62 (2025.01); H10D 48/362 (2025.01);
Abstract

The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.


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