The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2026
Filed:
Aug. 19, 2022
Intel Corporation, Santa Clara, CA (US);
Adel A. Elsherbini, Chandler, AZ (US);
Scott E. Siers, Alma, AR (US);
Gerald S. Pasdast, San Jose, CA (US);
Johanna M. Swan, Scottsdale, AZ (US);
Henning Braunisch, Phoenix, AZ (US);
Kimin Jun, Portland, OR (US);
Jiraporn Seangatith, Chandler, AZ (US);
Shawna M. Liff, Scottsdale, AZ (US);
Mohammad Enamul Kabir, Portland, OR (US);
Sathya Narasimman Tiagaraj, San Jose, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments of a microelectronic assembly comprise: a plurality of layers of IC dies, adjacent layers in the plurality of layers being coupled together by first interconnects and a package substrate coupled to the plurality of layers by second interconnects. A first layer in the plurality of layers comprises a dielectric material surrounding a first IC die in the first layer, a second layer in the plurality of layers is adjacent and non-coplanar with the first layer, the second layer comprises a first circuit region and a second circuit region separated by a third circuit region, the first circuit region and the second circuit region are bounded by respective guard rings, and the first IC die comprises conductive pathways conductively coupling conductive traces in the first circuit region with conductive traces in the second circuit region.