The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 2026
Filed:
Jun. 16, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Lung-Kun Chu, New Taipei City, TW;
Jia-Ni Yu, New Taipei City, TW;
Chun-Fu Lu, Hsinchu, TW;
Chung-Wei Hsu, Hsinchu County, TW;
Kuo-Cheng Chiang, Hsinchu County, TW;
Chih-Hao Wang, Hsinchu County, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
A semiconductor device and a manufacturing method thereof are provided. The method includes the following steps. A fin structure extending along a first direction and having a lower fin structure and an upper fin structure disposed over the lower fin structure is formed, the upper fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. A sacrificial gate structure extending along a second direction perpendicular to the first direction is formed over the upper fin structure. Gate spacers are formed on the sacrificial gate structure. A portion of the sacrificial gate structure is removed to expose the gate spacers. Portions of the exposed gate spacers are removed to form a first gate trench with a first dimension along the first direction. The rest of the sacrificial gate structure is removed to form a second gate trench with a second dimension along the first direction under the first gate trench, wherein the first dimension is greater than the second dimension. A gate dielectric and a first work function metal layer sequentially covering the first and second gate trenches are formed, wherein a first portion of the first work function metal layer merge in the second gate trench, and a second portion of the first work function metal layer is located on sidewalls of the first gate trench. The second portion of the first work function metal layer is removed to expose the gate dielectric located on sidewalls of the first gate trench while remaining the first portion of the first work function metal layer. A second work function metal layer is formed over the first portion of the first work function metal layer to fill the first gate trench.