The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2026

Filed:

Jan. 16, 2023
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Xinru Zeng, Wuhan, CN;

Peng Chen, Wuhan, CN;

Houde Zhou, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 80/00 (2023.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H10B 80/00 (2023.02); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 23/293 (2013.01); H01L 23/3135 (2013.01); H01L 23/49816 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/13 (2013.01); H01L 24/32 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/1601 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/48147 (2013.01); H01L 2224/73203 (2013.01); H01L 2224/73207 (2013.01); H01L 2224/73253 (2013.01); H01L 2924/1438 (2013.01);
Abstract

The present disclosure provides a memory system packaging structure and fabrication methods. The memory system packaging structure includes memory modules, a memory controller, a redistribution layer electrically connected to the memory controller, a plastic encapsulation layer encapsulating the memory modules and the memory controller, and one or more connecting pillars extending in the vertical direction and configured for providing electric power to the memory modules. Each memory module includes memory dies stacked in a vertical direction. Each connecting pillar includes a first portion being in physical contact with one of the memory dies and a second portion being in physical contact with the redistribution layer.


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