The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2026

Filed:

Jul. 05, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hsin-Yi Lee, Hsinchu, TW;

Shan-Mei Liao, Hsinchu, TW;

Kuo-Feng Yu, Hsinchu County, TW;

Da-Yuan Lee, Hsinchu County, TW;

Weng Chang, Hsinchu, TW;

Chi On Chui, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H01L 21/311 (2006.01); H01L 21/324 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H01L 21/31105 (2013.01); H01L 21/324 (2013.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01);
Abstract

A method of forming a semiconductor device includes forming a fin over a substrate, the fin comprising alternately stacking first semiconductor layers and second semiconductor layers, removing the first semiconductor layers to form spaces each between the second semiconductor layers, forming a gate dielectric layer wrapping around each of the second semiconductor layers, forming a fluorine-containing layer on the gate dielectric layer, performing an anneal process to drive fluorine atoms from the fluorine-containing layer into the gate dielectric layer, removing the fluorine-containing layer, and forming a metal gate on the gate dielectric layer.


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