The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2026

Filed:

Dec. 01, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chen-Hua Yu, Hsinchu, TW;

Chung-Hao Tsai, Huatan Township, TW;

Chuei-Tang Wang, Taichung, TW;

Yih Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H10B 12/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/3107 (2013.01); H01L 23/481 (2013.01); H01L 23/5283 (2013.01); H01L 24/05 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/82 (2013.01); H10B 12/02 (2023.02); H10B 12/315 (2023.02); H10B 12/50 (2023.02); H10N 50/01 (2023.02); H10N 50/80 (2023.02); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01);
Abstract

A package includes a memory stack attached to a logic device, the memory stack including first memory structures, a first redistribution layer over and electrically connected to the first memory structures, second memory structures on the first redistribution layer, a second redistribution layer over and electrically connected to the second memory structures, and first metal pillars on the first redistribution layer and adjacent the second memory structures, the first metal pillars electrically connecting the first redistribution layer and the second redistribution layer, wherein each first memory structure of the first memory structures includes a memory die comprising first contact pads and a peripheral circuitry die comprising second contact pads, wherein the first contact pads of the memory die are bonded to the second contact pads of the peripheral circuitry die.


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