The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2026

Filed:

Jul. 06, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Kenichi Sano, Hsinchu, TW;

Yi-Hsiu Chen, Taipei, TW;

Pinyen Lin, Rochester, NY (US);

Wei-Yen Woon, Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H10D 30/014 (2025.01); H10D 30/024 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/0188 (2025.01); H10D 84/0193 (2025.01); H10D 30/6211 (2025.01); H10D 30/6757 (2025.01); H10D 84/853 (2025.01);
Abstract

Methods of forming a metal gate structure of a stacked multi-gate device are provided. A method according to the present disclosure includes depositing a titanium nitride (TiN) layer over a channel region that includes bottom channel layers and top channel layers, depositing a dummy fill layer to cover sidewalls of the bottom channel layers, after the depositing of the dummy fill layer, selectively forming a blocking layer over the TiN layer along sidewalls of the top channel layers, selectively removing the dummy fill layer to release the bottom channel layers, selectively depositing a first work function metal layer to wrap around each of the bottom channel layers, forming a gate isolation layer over a top surface of the first work function metal layer, removing the blocking layer, releasing the top channel layers, and selectively depositing a second work function metal layer to wrap around each of the top channel layers.


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