The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2026

Filed:

May. 08, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shen-Yang Lee, Hsinchu, TW;

Hsiang-Pi Chang, Hsinchu, TW;

Huang-Lin Chao, Hsinchu, TW;

Pinyen Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 21/324 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H01L 21/324 (2013.01); H10D 30/014 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01);
Abstract

A method for fabricating a semiconductor device includes exposing one or more surfaces of a conduction channel of a transistor; overlaying the one or more surfaces with a dielectric interfacial layer; overlaying the dielectric interfacial layer with a blocking layer; performing a first annealing process to densify the dielectric interfacial layer; overlaying the blocking layer with a first high-k dielectric layer; forming one or more threshold voltage modulation layers over the first high-k dielectric layer; performing a second annealing process to adjust a doping profile of the first high-k dielectric layer; and overlaying the first high-k dielectric layer with a second high-k dielectric layer.


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