The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Jun. 25, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Nicholas Thomson, Hillsboro, OR (US);

Kalyan Kolluru, Portland, OR (US);

Ayan Kar, Portland, OR (US);

Rui MA, Portland, OR (US);

Benjamin Orr, Portland, OR (US);

Nathan Jack, Forest Grove, OR (US);

Biswajeet Guha, Hillsboro, OR (US);

Brian Greene, Portland, OR (US);

Lin Hu, Portland, OR (US);

Chung-Hsun Lin, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 86/00 (2025.01); H10D 89/60 (2025.01);
U.S. Cl.
CPC ...
H10D 86/00 (2025.01); H10D 89/611 (2025.01);
Abstract

Substrate-less lateral diode integrated circuit structures, and methods of fabricating substrate-less lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin or a stack of nanowires. A plurality of P-type epitaxial structures is over the fin or stack of nanowires. A plurality of N-type epitaxial structures is over the fin or stack of nanowires. One or more spacings are in locations over the fin or stack of nanowires, a corresponding one of the one or more spacings extending between neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.


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