The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 23, 2025
Filed:
Feb. 28, 2022
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Jung-Hung Chang, Changhua County, TW;
Lo-Heng Chang, Hsinchu, TW;
Zhi-Chang Lin, Zhubei, TW;
Shih-Cheng Chen, New Taipei, TW;
Kuo-Cheng Chiang, Zhubei, TW;
Chih-Hao Wang, Baoshan Township, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
A method of independently forming source/drain regions in NMOS regions including nanosheet field-effect transistors (NSFETs), NMOS regions including fin field-effect transistors (FinFETs) PMOS regions including NSFETs, and PMOS regions including FinFETs and semiconductor devices formed by the method are disclosed. In an embodiment, a device includes a semiconductor substrate; a first nanostructure over the semiconductor substrate; a first epitaxial source/drain region adjacent the first nanostructure; a first inner spacer layer adjacent the first epitaxial source/drain region, the first inner spacer layer comprising a first material; a second nanostructure over the semiconductor substrate; a second epitaxial source/drain region adjacent the second nanostructure; and a second inner spacer layer adjacent the second epitaxial source/drain region, the second inner spacer layer comprising a second material different from the first material.