The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 2025
Filed:
Dec. 06, 2021
Intel Corporation, Santa Clara, CA (US);
Kimin Jun, Portland, OR (US);
Adel A. Elsherbini, Tempe, AZ (US);
Christopher M. Pelto, Beaverton, OR (US);
Georgios Dogiamis, Chandler, AZ (US);
Bradley A. Jackson, Lake Oswego, OR (US);
Shawna M. Liff, Scottsdale, AZ (US);
Johanna M. Swan, Scottsdale, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments of the present disclosure provide a microelectronic assembly comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer; and a third layer between the first layer and the second layer, the third layer comprising conductive routing traces in a dielectric. A first interface is between the first layer and the third layer and includes first interconnects having a first pitch of less than 10 micrometers between adjacent ones of the first interconnects, a second interface is between the second layer and the third layer and includes second interconnects having a second pitch of less than 10 micrometers between adjacent ones of the second interconnects, and the routing traces in the third layer are to provide lateral electrical coupling between the first interconnects and the second interconnects.