The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Apr. 29, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hsin-Yen Huang, New Taipei, TW;

Shao-Kuan Lee, Kaohsiung, TW;

Cheng-Chin Lee, Taipei, TW;

Hai-Ching Chen, Hsinchu, TW;

Shau-Lin Shue, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/5283 (2013.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01);
Abstract

An interconnect structure is provided. The interconnect structure includes a first metal line and a second metal line in a first dielectric layer, a catalyst layer on the first dielectric layer, a dielectric block on the catalyst layer, an etching stop layer along the second metal line, the catalyst layer and the dielectric block, a second dielectric layer over the etching stop layer, and a first via through the second dielectric layer and the etching stop layer on the first metal line. A first interface between the etching stop layer and the second metal line is level to a second interface between the catalyst layer and the first dielectric layer.


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