The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2025

Filed:

Aug. 21, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chih-Hsin Lu, Tainan, TW;

Chung-Hao Tsai, Changhua County, TW;

Chuei-Tang Wang, Taichung, TW;

Chen-Hua Yu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 24/08 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/5286 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 2224/05016 (2013.01); H01L 2224/05556 (2013.01); H01L 2224/05576 (2013.01); H01L 2224/0801 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/13026 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06568 (2013.01); H01L 2924/1011 (2013.01); H01L 2924/10157 (2013.01);
Abstract

A semiconductor package structure and a manufacturing method thereof is provided. The semiconductor package includes a first semiconductor die, including a semiconductor substrate and a first interconnect structure disposed on the semiconductor substrate; a second semiconductor die disposed on and electrically connected to the first semiconductor die, including a second semiconductor substrate and a second interconnect structure; a third interconnect structure, where in the second interconnect structure and the third interconnect structure are disposed on opposite sides of the second semiconductor substrate, and wherein the second interconnect structure is between the first interconnect structure and the third interconnect structure.


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