The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2025
Filed:
Mar. 13, 2024
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Chun Hsiung Tsai, Xinpu Township, TW;
Yu-Ming Lin, Hsinchu, TW;
Kuo-Feng Yu, Zhudong Township, TW;
Ming-Hsi Yeh, Hsinchu, TW;
Shahaji B. More, Hsinchu, TW;
Chandrashekhar Prakash Savant, Hsinchu, TW;
Chih-Hsin Ko, Fongshan, TW;
Clement Hsingjen Wann, Carmel, NY (US);
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3065 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/324 (2006.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H01L 21/3065 (2013.01); H01L 21/02057 (2013.01); H01L 21/30604 (2013.01); H01L 21/324 (2013.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01);
Abstract
In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.