The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Feb. 23, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Kai-Hsuan Lee, Hsinchu, TW;

Shih-Che Lin, Hsinchu, TW;

Po-Yu Huang, Hsinchu, TW;

Shih-Chieh Wu, Hsinchu, TW;

I-Wen Wu, Hsinchu, TW;

Chen-Ming Lee, Taoyuan, TW;

Fu-Kai Yang, Hsinchu, TW;

Mei-Yun Wang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/0147 (2025.01); H10D 84/038 (2025.01);
Abstract

A semiconductor structure includes a substrate, nanostructures over the substrate, and a gate structure wrapping around the nanostructures. The gate structure includes a gate dielectric layer and a gate electrode wrapping around the gate dielectric layer. The semiconductor structure further includes a source/drain feature in contact with the nanostructures, a contact etch stop layer over the source/drain feature, and a seal layer over the air spacer and the gate structure, and on a sidewall of the contact etch stop layer. The contact etch stop layer is separated from the gate structure by an air spacer.


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