The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Feb. 10, 2023
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Liang-An Huang, Tainan, TW;

Ming-Hua Tsai, Tainan, TW;

Wen-Fang Lee, Hsinchu, TW;

Chin-Chia Kuo, Tainan, TW;

Jung Han, New Taipei, TW;

Chun-Lin Chen, Tainan, TW;

Ching-Chung Yang, Hsinchu, TW;

Nien-Chung Li, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/60 (2025.01); H10D 30/64 (2025.01); H10D 62/17 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10D 30/603 (2025.01); H10D 30/64 (2025.01); H10D 62/235 (2025.01); H10D 64/514 (2025.01); H10D 64/516 (2025.01);
Abstract

An extended drain metal oxide semiconductor transistor includes a substrate. A gate is disposed on the substrate. A source doped region is disposed in the substrate at one side of the gate. A drain doped region is disposed in the substrate at another side of the gate. A thin gate dielectric layer is disposed under the gate. A thick gate dielectric layer is disposed under the gate. The thick gate dielectric layer extends from the bottom of the gate to contact the drain doped region. A second conductive type first well is disposed in the substrate and surrounds the source doped region and the drain doped region. A deep well is disposed within the substrate and surrounds the second conductive type first well.


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