The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Feb. 29, 2024
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Edward Fuergut, Dasing, DE;

Achim Althaus, Regensburg, DE;

Martin Gruber, Schwandorf, DE;

Marco Nicolas Mueller, Villach, AT;

Bernd Schmoelzer, Radenthein, AT;

Wolfgang Scholz, Olching, DE;

Mark Thomas, Bodensdorf, AT;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/485 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/13 (2006.01); H01L 23/14 (2006.01); H01L 23/495 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/485 (2013.01); H01L 21/56 (2013.01); H01L 23/3135 (2013.01); H01L 23/13 (2013.01); H01L 23/142 (2013.01); H01L 23/49548 (2013.01); H01L 23/49861 (2013.01);
Abstract

A method for fabricating a semiconductor device includes: providing a die carrier; disposing a semiconductor die on a main face of the die carrier, the semiconductor die having one or more contact pads; applying an encapsulant at least partially to the semiconductor die and at least a portion of the main face of the die carrier; applying an insulation layer to the encapsulant; and fabricating electrical interconnects by forming openings into the encapsulant and the insulation layer and filling a conductive material into the openings. Additional methods for fabricating a semiconductor device are described.


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