The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2025

Filed:

Jul. 31, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chia-Yu Wei, Hsinchu, TW;

Fu-Cheng Chang, Hsinchu, TW;

Hsin-Chi Chen, Hsinchu, TW;

Ching-Hung Kao, Hsinchu, TW;

Chia-Pin Cheng, Hsinchu, TW;

Kuo-Cheng Lee, Hsinchu, TW;

Hsun-Ying Huang, Hsinchu, TW;

Yen-Liang Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10F 39/00 (2025.01); H10D 30/60 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 64/27 (2025.01); H10F 39/18 (2025.01);
U.S. Cl.
CPC ...
H10F 39/80373 (2025.01); H10D 30/60 (2025.01); H10D 30/6212 (2025.01); H10D 62/116 (2025.01); H10D 64/513 (2025.01); H10D 64/518 (2025.01); H10F 39/18 (2025.01);
Abstract

A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures. The semiconductor device further includes a gate structure. The gate structure includes a first sidewall and a second sidewall angled with respect to the first sidewall. The gate structure further includes a first surface extending between the first sidewall and the second sidewall, wherein a dimension of the gate structure in a first direction is less than a dimension of each of the plurality of isolation structures in the first direction.


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