The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 28, 2025
Filed:
Jun. 25, 2021
Device, method and system to mitigate stress on hybrid bonds in a multi-tier arrangement of chiplets
Intel Corporation, Santa Clara, CA (US);
Kimin Jun, Portland, OR (US);
Feras Eid, Chandler, AZ (US);
Adel Elsherbini, Tempe, AZ (US);
Aleksandar Aleksov, Chandler, AZ (US);
Shawna Liff, Scottsdale, AZ (US);
Johanna Swan, Scottsdale, AZ (US);
Julien Sebot, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Techniques and mechanisms for mitigating stress on hybrid bonded interfaces in a multi-tier arrangement of integrated circuit (IC) dies. In an embodiment, first dies are bonded at a host die each via a respective one of first hybrid bond interfaces, wherein a second one or more dies are coupled to the host die each via a respective one of the first dies, and via a respective second hybrid bond interface. Stress at one of the hybrid bond interfaces is mitigated by properties of a first dielectric layer that extends to that hybrid bond interface. In another embodiment, stress at a given one of the hybrid bond interfaces is mitigated by properties of a dummy chip—or alternatively, properties of a patterned encapsulation structure—which is formed on the given hybrid bond interface.