The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 2025
Filed:
Jun. 16, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Che-Lun Chang, Hsinchu, TW;
Kuan-Ting Pan, Taipei, TW;
Wei-Yang Lee, Taipei, TW;
Chia-Pin Lin, Xinpu Township, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed over a substrate, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure is etched thereby forming a source/drain space, ends of the first semiconductor layers is laterally etched, an insulating layer is formed on a sidewall of the source/drain space, the insulating layer is partially etched, thereby forming one or more inner spacers on an etched end face of each of one or more first semiconductor layers and leaving a part of the insulating layer as a remaining insulating layer, and a source/drain epitaxial layer is formed in the source/drain space. After the source/drain epitaxial layer is formed, an end face of at least one of the second semiconductor layers is covered by the remaining insulating layer.