The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2025

Filed:

Aug. 13, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Kai-Hsuan Lee, Hsinchu, TW;

Shih-Che Lin, Hsinchu, TW;

Po-Yu Huang, Hsinchu, TW;

Shih-Chieh Wu, Hsinchu, TW;

I-Wen Wu, Hsinchu, TW;

Chen-Ming Lee, Taoyuan County, TW;

Fu-Kai Yang, Hsinchu, TW;

Mei-Yun Wang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H01L 21/02 (2006.01); H01L 21/764 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H01L 21/0259 (2013.01); H01L 21/764 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0188 (2025.01); H10D 84/85 (2025.01);
Abstract

Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes receiving a fin-shaped structure comprising a first channel region and a second channel region, a first and a second dummy gate structures disposed over the first and the second channel regions, respectively. The method also includes removing a portion of the first dummy gate structure, a portion of the first channel region and a portion of the substrate under the first dummy gate structure to form a trench, forming a hybrid dielectric feature in the trench, removing a portion of the hybrid dielectric feature to form an air gap, sealing the air gap, and replacing the second dummy gate structure with a gate stack after sealing the air gap.


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