The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

May. 04, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Pei-Ling Kao, Tainan, TW;

You-Ting Lin, Miaoli County, TW;

Chih-Chung Chang, Nantou County, TW;

Jiun-Ming Kuo, Taipei, TW;

Yuan-Ching Peng, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/3115 (2006.01); H01L 21/32 (2006.01); H01L 21/324 (2006.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H01L 21/0259 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/31155 (2013.01); H01L 21/32 (2013.01); H01L 21/324 (2013.01); H10D 30/031 (2025.01); H10D 30/611 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/0188 (2025.01); H10D 84/85 (2025.01); H10D 30/024 (2025.01); H10D 84/0193 (2025.01);
Abstract

A method includes providing a semiconductor substrate having a first region and a second region, epitaxially growing a semiconductor layer above the semiconductor substrate, patterning the semiconductor layer to form a first fin in the first region and a second fin in the second region, and depositing a dielectric material layer on sidewalls of the first and second fins. The method also includes performing an anneal process in driving dopants into the dielectric material layer, such that a dopant concentration in the dielectric material layer in the first region is higher than that in the second region, and performing an etching process to recess the dielectric material layer, thereby exposing the sidewalls of the first and second fins. A top surface of the recessed dielectric material layer in the first region is lower than that in the second region.


Find Patent Forward Citations

Loading…