The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Feb. 28, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Fa-Shen Jiang, Taoyuan, TW;

Hsia-Wei Chen, Taipei, TW;

Hsun-Chung Kuang, Hsinchu, TW;

Hai-Dang Trinh, Hsinchu, TW;

Cheng-Yuan Tsai, Chu-Pei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); G11C 11/56 (2006.01); H10B 53/30 (2023.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01);
U.S. Cl.
CPC ...
G11C 11/161 (2013.01); G11C 11/1657 (2013.01); G11C 11/1659 (2013.01); G11C 11/5614 (2013.01); G11C 11/5657 (2013.01); G11C 11/5678 (2013.01); H10B 53/30 (2023.02); H10B 61/22 (2023.02); H10B 63/30 (2023.02);
Abstract

Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.


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