The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2025

Filed:

Aug. 30, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Yu-Wei Jiang, Hsinchu, TW;

Hung-Chang Sun, Kaohsiung, TW;

Sheng-Chih Lai, Hsinchu County, TW;

Kuo-Chang Chiang, Hsinchu, TW;

Tsuching Yang, Taipei, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/27 (2023.01); H01L 23/522 (2006.01); H10B 41/10 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 23/5226 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02);
Abstract

A semiconductor memory structure includes a plurality of gate layers and a plurality of insulating layers alternately stacked over a substrate, and at least an active column disposed over the substrate. The gate layers and the insulating layers are alternately stacked along a first direction. The active column extends along the first direction and penetrates the gate layer and the insulating layer. The active column includes a central portion, a charge-trapping layer surrounding the central portion, and a channel layer between the central portion and the charge-trapping layer. The central portion of the active column includes an isolation structure, a source structure and a drain structure. The source structure and the drain structure are disposed at two sides of the isolation structure.


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