The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

May. 24, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chung-Wei Hsu, Hsinchu, TW;

Kuo-Cheng Chiang, Hsinchu County, TW;

Mao-Lin Huang, Hsinchu, TW;

Lung-Kun Chu, New Taipei, TW;

Jia-Ni Yu, Hsinchu, TW;

Kuan-Lun Cheng, Hsinchu, TW;

Chih-Hao Wang, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H10D 30/6735 (2025.01); H10D 62/119 (2025.01); H10D 84/0172 (2025.01); H10D 84/0181 (2025.01); H10D 84/85 (2025.01);
Abstract

A method includes providing a first channel layer of a first transistor and a second channel layer of a second transistor over a substrate, forming a dipole layer over the first channel layer and the second channel layer, forming a patterned hard mask covering the second channel layer and exposing the first channel layer, removing the dipole layer from the first channel layer, removing the patterned hard mask, performing a thermal drive-in process, forming an interfacial dielectric layer on the first channel layer and the dipole layer, and forming a high-k dielectric layer on the interfacial dielectric layer. The dipole layer includes a p-dipole material.


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