The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

May. 11, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Wei-Min Liu, Hsinchu, TW;

Cheng-Yen Wen, Taichung, TW;

Li-Li Su, Chubei, TW;

Chii-Horng Li, Zhubei, TW;

Yee-Chia Yeo, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/66 (2025.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 64/679 (2025.01); H01L 21/0259 (2013.01); H01L 21/28123 (2013.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/018 (2025.01);
Abstract

A method includes forming a stack of layers, which includes a plurality of semiconductor nano structures and a plurality of sacrificial layers. The plurality of semiconductor nano structures and the plurality of sacrificial layers are arranged alternatingly. The method further includes laterally recessing the plurality of sacrificial layers to form lateral recesses, forming inner spacers in the lateral recesses, and epitaxially growing a source/drain region from the plurality of semiconductor nano structures. The source/drain region is spaced apart from the inner spacers by air inner spacers.


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