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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12394624 B1

PDFFull Text
Date of Patent:
Aug. 19, 2025

Filed:

Dec. 12, 2022

Silicon intermixing layer for blocking diffusion

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chun-Chieh Wang, Kaohsiung, TW;

Yueh-Ching Pai, Taichung, TW;

Kuo-Jung Huang, Hsinchu, TW;

Huai-Tei Yang, Hsinchu, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

Ori Nadav

Int. Cl.
CPC ...
H01L 21/28 (2025.01); H01L 21/02 (2006.01); H01L 21/308 (2006.01); H01L 21/768 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H01L 21/28088 (2013.01); H01L 21/0228 (2013.01); H01L 21/28194 (2013.01); H01L 21/3086 (2013.01); H01L 21/76829 (2013.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 64/017 (2025.01); H10D 64/667 (2025.01); H10D 84/0135 (2025.01); H10D 84/0147 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01);
Abstract

A method of forming an integrated circuit structure includes forming a gate dielectric on a wafer, forming a work function layer over the gate dielectric, depositing a capping layer over the work function layer, soaking the capping layer in a silicon-containing gas to form a silicon-containing layer, forming a blocking layer after the silicon-containing layer is formed, and forming a metal-filling region over the blocking layer.

Find Patent Forward Citations

Wang, Chun-Chieh. (2025). Silicon intermixing layer for blocking diffusion (U.S. Patent No. 12394624). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12394624

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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