The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2025

Filed:

Jun. 28, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Hsinchu, TW;

Inventors:

Hsien-Wen Liu, Hsinchu, TW;

Shih-Ting Hung, Sanchong, TW;

Jyun-Lin Wu, Hsinchu, TW;

Yao-Chun Chuang, Hsinchu, TW;

Yinlung Lu, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 3/22 (2006.01); B23K 1/00 (2006.01); B23K 101/42 (2006.01); H05K 1/18 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H05K 3/225 (2013.01); B23K 1/0016 (2013.01); H05K 1/181 (2013.01); H05K 3/341 (2013.01); B23K 2101/42 (2018.08); H05K 2201/09136 (2013.01);
Abstract

Methods for improving joinder between a surface-mount package and a printed circuit board are disclosed. The warpage at a corner of the surface-mount package and at a corresponding corner of a joint area on the printed circuit board are measured to determine the degree of mismatch. A mini-pad is applied to the corner between the surface-mount package and the joint area on the printed circuit board. The thickness of the mini-pad pushes against the surface-mount package and the printed circuit board, reducing the degree of mismatch below a critical dimension of a ball grid array of the surface-mount package. The surface-mount package can then be soldered to the joint area, reducing or preventing the formation of solder bridges and short circuits.


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