The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Nov. 22, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yu-Kuan Lin, Hsinchu, TW;

Chang-Ta Yang, Hsinchu, TW;

Ping-Wei Wang, Hsinchu, TW;

Kuo-Yi Chao, Hsinchu, TW;

Mei-Yun Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 10/00 (2023.01); G11C 11/412 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H10D 30/01 (2025.01); H10D 89/10 (2025.01);
U.S. Cl.
CPC ...
H10B 10/12 (2023.02); G11C 11/412 (2013.01); H01L 21/76895 (2013.01); H01L 23/5226 (2013.01); H10B 10/18 (2023.02); H10D 30/021 (2025.01); H10D 89/10 (2025.01);
Abstract

An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.


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