The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

May. 05, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Wei-Han Fan, Hsin-Chu, TW;

Chia-Pin Lin, Hsinchu County, TW;

Wei-Yang Lee, Taipei, TW;

Tzu-Hua Chiu, Hsinchu, TW;

Kuan-Hao Cheng, Hsinchu, TW;

Po Shao Lin, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/66 (2025.01); H01L 21/02 (2006.01); H01L 21/28 (2025.01); H01L 21/285 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/62 (2025.01);
U.S. Cl.
CPC ...
H10D 64/679 (2025.01); H01L 21/0259 (2013.01); H01L 21/28123 (2013.01); H01L 21/28518 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 64/62 (2025.01);
Abstract

A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, and a source/drain feature disposed over the substrate and coupled to the vertical stack of channel members. The source/drain feature is spaced apart from a sidewall of the gate structure by an air gap and a dielectric layer, and the air gap extends into the source/drain feature.


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