The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Jun. 27, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Wei Jiang, Hsinchu, TW;

Sheng-Chih Lai, Hsinchu County, TW;

Tsuching Yang, Taipei, TW;

Hung-Chang Sun, Kaohsiung, TW;

Kuo-Chang Chiang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 51/20 (2023.01); H10B 51/10 (2023.01); H10B 51/30 (2023.01); H10D 62/80 (2025.01);
U.S. Cl.
CPC ...
H10B 51/20 (2023.02); H10B 51/10 (2023.02); H10B 51/30 (2023.02); H10D 62/80 (2025.01);
Abstract

A memory device includes a multi-layer stack, a channel layer, a memory material layer and a memory material layer. The multi-layer stack includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately along a first direction. The memory material layer is disposed between the channel layer and each of the conductive layers and the dielectric layers. The conductive pillars extend in the first direction, wherein the at least three conductive pillars are aligned along a second direction substantially perpendicular to the first direction.


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