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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12362307 B1

PDFFull Text
Date of Patent:
Jul. 15, 2025

Filed:

Aug. 30, 2022

Semiconductor package with ball grid array connection having improved reliability

Applicant:

Taiwan Semiconductor Manufacturing Company, Hsinchu, TW;

Inventors:

Yu-Sheng Lin, Zhubei, TW;

Chen-Nan Chiu, Hsinchu, TW;

Jyun-Lin Wu, Hsinchu, TW;

Yao-Chun Chuang, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

Lippes Mathias LLP

Primary Examiner:

Douglas W Owens

Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 23/367 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 24/17 (2013.01); H01L 21/4882 (2013.01); H01L 23/3675 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 25/0655 (2013.01); H01L 2224/05547 (2013.01); H01L 2224/05551 (2013.01); H01L 2224/05555 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/06051 (2013.01); H01L 2224/06179 (2013.01); H01L 2224/16014 (2013.01); H01L 2224/16055 (2013.01); H01L 2224/16059 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/17055 (2013.01); H01L 2224/17179 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/81375 (2013.01); H01L 2224/81395 (2013.01); H01L 2224/81815 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/16195 (2013.01); H01L 2924/16235 (2013.01); H01L 2924/16251 (2013.01); H01L 2924/1631 (2013.01); H01L 2924/1632 (2013.01); H01L 2924/3511 (2013.01); H01L 2924/3512 (2013.01);
Abstract

A semiconductor package includes a substrate and at least one integrated circuit (IC) die. Substrate solder resist has substrate solder resist openings exposing substrate bonding pads of the bonding surface of the substrate, and die solder resist has aligned die solder resist openings exposing die bonding pads of the bonding surface of the IC die. A ball grid array (BGA) electrically connects the die bonding pads with substrate bonding pads via the die solder resist openings and the substrate solder resist openings. The die solder resist openings include a subset A of the die solder resist openings in a region A of the bonding surface of the IC die and a subset B of the die solder resist openings in a region B of the bonding surface of the IC die. The die solder resist openings of subset A are larger than those of subset B.

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