The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Jul. 26, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Shih-Kang Fu, Taoyuan County, TW;

Ming-Han Lee, Taipei, TW;

Shau-Lin Shue, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/321 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01);
U.S. Cl.
CPC ...
H01L 21/7684 (2013.01); H01L 21/3212 (2013.01); H01L 21/76805 (2013.01); H01L 21/76829 (2013.01); H01L 21/76832 (2013.01); H01L 21/76841 (2013.01); H01L 21/76843 (2013.01); H01L 21/76895 (2013.01); H01L 23/53209 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53252 (2013.01); H01L 23/535 (2013.01);
Abstract

A semiconductor structure includes a contact over a substrate, an interlayer dielectric (ILD) layer including a first region disposed directly above the contact and a second region disposed adjacent to the first region, first conductive features embedded in the first region and separated by a first distance, a dielectric layer embedded in the ILD layer and disposed between the first conductive features in the first region, and second conductive features disposed in the second region and separated by a second distance greater than the first distance. The second region is free of the dielectric layer.


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