The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2025
Filed:
Sep. 20, 2021
Intel Corporation, Santa Clara, CA (US);
Ashish Verma Penumatcha, Beaverton, OR (US);
Uygar E. Avci, Portland, OR (US);
Chelsey Dorow, Portland, OR (US);
Tanay Gosavi, Portland, OR (US);
Chia-Ching Lin, Portland, OR (US);
Carl Naylor, Portland, OR (US);
Nazila Haratipour, Portland, OR (US);
Kevin P. O'Brien, Portland, OR (US);
Seung Hoon Sung, Portland, OR (US);
Ian A. Young, Olympia, WA (US);
Urusa Alaan, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Thin film transistors having semiconductor structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a two-dimensional (2D) material layer above a substrate. A gate stack is above the 2D material layer, the gate stack having a first side opposite a second side. A semiconductor structure including germanium is included, the semiconductor structure laterally adjacent to and in contact with the 2D material layer adjacent the first side of the gate stack. A first conductive structure is adjacent the first side of the second gate stack, the first conductive structure over and in direct electrical contact with the semiconductor structure. The semiconductor structure is intervening between the first conductive structure and the 2D material layer. A second conductive structure is adjacent the second side of the second gate stack, the second conductive structure over and in direct electrical contact with the 2D material layer.