The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2025

Filed:

Jun. 30, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chen-Hua Yu, Hsinchu, TW;

Tzu Yun Huang, Taipei, TW;

Ming-Che Ho, Tainan, TW;

Hung-Jui Kuo, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/16 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/4857 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 21/78 (2013.01); H01L 23/16 (2013.01); H01L 23/3121 (2013.01); H01L 23/3128 (2013.01); H01L 23/49822 (2013.01); H01L 23/5383 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 24/48 (2013.01); H01L 2224/48227 (2013.01); H01L 2225/1058 (2013.01);
Abstract

In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die; and a redistribution structure including: a plurality of dielectric layers over the encapsulant and the integrated circuit die; a plurality of metallization patterns in the dielectric layers, the metallization patterns being electrically coupled to the integrated circuit die; and a sealing ring in the dielectric layers, the sealing ring extending around the metallization patterns, the sealing ring being electrically isolated from the metallization patterns and the integrated circuit die, the sealing ring including a plurality of sealing ring layers, each of the sealing ring layers including a via portion extending through a respective one of the dielectric layers, the via portion of each of the sealing ring layers being aligned along a same common axis.


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