The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2025
Filed:
Jun. 13, 2022
Applicant:
Yangtze Memory Technologies Co., Ltd., Wuhan, CN;
Inventors:
Chuanhai Shan, Wuhan, CN;
Zhaosong Li, Wuhan, CN;
Zhouyang Lu, Wuhan, CN;
Jing Liu, Wuhan, CN;
Jing Gao, Wuhan, CN;
Assignee:
Yangtze Memory Technologies Co., Ltd., Wuhan, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2223/54426 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/8013 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01);
Abstract
Three-dimensional (3D) NAND memory devices and methods are provided. A fabrication method includes forming a semiconductor layer over a substrate, forming an opening that extends partially through the semiconductor layer, depositing a first stack layer and a second stack layer that are alternately stacked over a sidewall of the opening and over the semiconductor layer, and filling the opening with a dielectric material to form an alignment mark.