The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

Dec. 23, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Srikant Nekkanty, Chandler, AZ (US);

Debendra Mallik, Chandler, AZ (US);

Joe F. Walczyk, Tigard, OR (US);

Saikumar Jayaraman, Hillsboro, OR (US);

Feroz Mohammad, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01R 13/11 (2006.01); H01L 23/00 (2006.01); H01L 23/532 (2006.01); H01L 25/075 (2006.01); H01R 12/58 (2011.01);
U.S. Cl.
CPC ...
H01R 13/11 (2013.01); H01L 23/53228 (2013.01); H01L 24/14 (2013.01); H01L 25/075 (2013.01); H01R 12/58 (2013.01);
Abstract

Embodiments described herein may be related to apparatuses, processes, and techniques related to micro socket arrays with fine pitch contacts to electrically couple dies, in particular photonics dies, within multichip photonics packages. In embodiments, micro socket arrays may be used in conjunction with multichip module packaging that include silicon photonic engines and optical fiber modules on the same package. In embodiments, these packages may also use a system on chip (SOC), as well as fine pitch die to die connections, for example an EMIB, that may be used to connect a PIC with an SOC. Other embodiments may be described and/or claimed.


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