The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

Jun. 27, 2024
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Sung-Li Wang, Hsinchu County, TW;

Hung-Yi Huang, Hsin-chu, TW;

Yu-Yun Peng, Hsinchu, TW;

Mrunal A. Khaderbad, Hsinchu, TW;

Chia-Hung Chu, Taipei, TW;

Shuen-Shin Liang, Hsinchu County, TW;

Keng-Chu Lin, Ping-Tung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/265 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01); H10D 64/23 (2025.01);
U.S. Cl.
CPC ...
H01L 21/26586 (2013.01); H01L 21/76804 (2013.01); H01L 21/76805 (2013.01); H01L 21/7684 (2013.01); H01L 21/76862 (2013.01); H01L 21/76864 (2013.01); H01L 21/76877 (2013.01); H01L 21/76883 (2013.01); H01L 21/76895 (2013.01); H01L 23/53209 (2013.01); H01L 23/53242 (2013.01); H01L 23/53257 (2013.01); H01L 23/535 (2013.01); H10D 64/256 (2025.01); H01L 2221/1068 (2013.01);
Abstract

A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.


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