The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2025

Filed:

Jan. 05, 2024
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Lung-Kun Chu, Hsinchu, TW;

Mao-Lin Huang, Hsinchu, TW;

Chung-Wei Hsu, Hsinchu, TW;

Jia-Ni Yu, Hsinchu, TW;

Kuo-Cheng Chiang, Hsinchu, TW;

Kuan-Lun Cheng, Hsinchu, TW;

Chih-Hao Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/01 (2025.01); H10D 30/67 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 84/0128 (2025.01); H10D 30/6735 (2025.01); H10D 84/0144 (2025.01); H10D 84/038 (2025.01);
Abstract

A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.


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