The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2025

Filed:

Apr. 18, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Aurelien Gauthier Brun, Hsin-Chu, TW;

Chun Lin Tsai, Hsin-Chu, TW;

Jiun-Lei Jerry Yu, Zhudong Township, TW;

Po-Chih Chen, Hsinchu, TW;

Yun-Hsiang Wang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 64/23 (2025.01); H10D 30/47 (2025.01); H10D 64/00 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10D 64/257 (2025.01); H10D 30/475 (2025.01); H10D 64/01 (2025.01); H10D 64/111 (2025.01); H10D 64/519 (2025.01);
Abstract

The present disclosure relates to a transistor device. The transistor device includes a plurality of source contacts disposed over a substrate. A plurality of gate structures are disposed over the substrate. The plurality of gate structures wrap around one or more of the plurality of source contacts in one or more closed loops. A drain contact is disposed over the substrate. The drain contact continuously wraps around one or more of the plurality of gate structures as a continuous structure. The plurality of gate structures are separated from the drain contact by a first distance and are separated from a source contact of the plurality of source contacts by a second distance. The second distance is different than the first distance.


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